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Brief technical analysis required before assessing current technology and is to come in the storage of the future.
For the novices or beginners can seem that all memory chips within the SSD may be the same. But that statement could not be further from reality: 2-bit MLC, 3-bit MLC (TLC), synchronous, asynchronous, SLC, ONFI 1.0 and ONFI 2.0 … consumer may seem a silly
The expansion of SSD brings progress and improvements at a rate very fast and the decision to purchase is increasingly complicated. Before understanding the parts and operation of an SSD must understand why a NAND memory and its manufacturing process
A short introduction
The NAND flash memory stores data in a cell array memory using floating gate transistors. There are two gates, the Gate Control (GC, Gate Control, above) and the floating gate (FG, Floating Gate, below) isolated by an oxide layer.
The electrons flow freely between the door control (CG) and channel (Channel). When a voltage is applied to any entity, electrons are drawn in the sense that the voltage is applied, so that, to program a cell, a voltage is applied at the CG, which attracts electrons up.
The floating gate, which is electrically isolated by an insulating layer traps electrons as they pass through on the way to the control gate. can stay there years under normal operating conditions .
To clear the cell, a voltage is applied in the opposite direction (the channel) while control gate is grounded, repelling electrons from the floating gate to the channel.
To check the status of a cell, a high voltage is applied to the control gate (GC). If the floating gate keeps a certain charge (electrons are trapped there), the threshold voltage of the cell is altered, affecting the signal emanating from the control gate as it moves through the canal. The amount of current required to complete the circuit determines the state of the cell.
This electrical activity wears the physical structure of the cell with the passage of time . Therefore, each cell has a finite lifetime, measured in terms understandable by the consumer in cycles programmed and erase (P / E cycles) and are directly related to the geometry of the process (production engineering) and the number of stores each bit cell. NAND storage complexity requires some additional processes, including a manager of bad blocks, the garbage collector and the correction of errors. All managed by the firmware of the SSD
- . Note: it is important to always actualicéis possible firmware, is an important element in the performance of SSD
SLC, MLC and TLC NAND
The NAND technology has progressed rapidly in line with the high demands of consumers and industry. For explaining the simplest possible way to understand the data stored in a NAND flash memory is represented by an electric charge stored in each cell. The difference between a NAND Sigle-Level-Cell (SLC) and Multi-Level-Cell (MLC) is the number of bits that can store that cell at the same time , ie levels are distinguished in the burden of that cell and values that a 1 or a 0. The NAND SLC reads can only store one bit of information per cell. As their names suggest NAND MLC can store two bits of data or 3 bits of data.
To understand it’ll represent the cells as a “hub” of electrons.
technology to discern the data is becoming more complex values we want to store and read . Schedule a cell with 3 bits (TLC) is more difficult than with 1 bit (SLC).
Advantages of NAND MLC
The more bits can be stored at the same time, more data capacity will be in the same space, reducing manufacturing costs and increasing production capacity and the NAND. This phenomenon allowed and allows NAND flash memories are increasingly present in the devices we use. As you can guess all of SSD sold today have MLC NAND (2 bit) or TLC (bit 3).
Improved amount of information that can be stored in the same space is extremely simple to illustrate:
Imagine a SSD 16Gb SLC NAND (16 billion bits or cells). If these chips were 2-bit MLC would have a storage capacity of 32GB and 48GB if it were TLC. Same space and approximate cost of manufacture.
Limitations of the NAND MLC
Of course, add more bits in each cell makes it more difficult to distinguish between states of the same , which reduces the reliability, endurance and memory performance. Determining whether a “container” is full or empty (SLC) is much easier to determine if a full bathroom, complete medium, three quarters full or completely full (MLC). It may take up to 4 times longer to write and up to 2.5 times longer to read MLC NAND memories 3 bits than its predecessor SLC.
Another side effect of storing more bits per cell is increased ratio degradation thereof . The status of each NAND cell is determined by the number of electrons in the floating gate. The oxide layers that trap electrons in the floating gate wear out every programming and erasing the cell. With heavy wear, electrons begin to escape more often. This was no problem in SLC NAND since the state was full or empty. But cells with multi state accuracy is very important, especially in 3-bit 8 states need to differentiate between. The problem is that the oxide layer becomes smaller and smaller with every technological progress. Less oxide layer is lower lifetime of that memory.
today NAND, NAND future
Semiconductor manufacturers are making great strides in a short time to alleviate the problems generated using the NAND technology. Manufacturers like Samsung, one of the leaders in the development and manufacture of semiconductors, drivers have achieved a sublime performance that not only fail to worse performance compared to the SLC SSD technology, but increased performance each year. The latest SSDs demonstrate that performance and capabilities we thought would arrive within many years are already available to consumers .
March 26, 2015
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